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IW4042BD especificación: Quad cloced D latch, high-voltage silicon-gate CMOS
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IW4042BD Datasheet y Espec
Fabricante : Integral
Embalaje : SOIC
Pins : 16
Temperatura : Min -55 °C | Max 125 °C
Tamaño : 194 KB
Aplicación : Quad cloced D latch, high-voltage silicon-gate CMOS
IW4042BD PDF Download