Path:OKDatasheet > Datasheet Semiconductor > Lattice Datasheet > M5LV-128/74-7VI
M5LV-128/74-7VI especificación: 7ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
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M5LV-128/74-7VI Datasheet y Espec
Fabricante : Lattice
Embalaje : TQFP
Pins : 100
Temperatura : Min -40 °C | Max 85 °C
Tamaño : 1126 KB
Aplicación : 7ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
M5LV-128/74-7VI PDF Download