Path:OKDatasheet > Datasheet Semiconductor > Lattice Datasheet > M5LV-512/120-6YC
M5LV-512/120-6YC especificación: 6ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
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M5LV-512/120-6YC Datasheet y Espec
Fabricante : Lattice
Embalaje : PQFP
Pins : 100
Temperatura : Min 0 °C | Max 70 °C
Tamaño : 1126 KB
Aplicación : 6ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
M5LV-512/120-6YC PDF Download